1. Field of the Invention
The present invention relates to an analog-to-digital converter receiving an analog input voltage to be converted into a digital output signal, comprising:
a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of voltages referred to as reference voltages on the nodes between them, PA1 a stage of comparators, each comparing the analog input voltage with one of the reference voltages, PA1 a memory stage comprising memory elements referred to as memory cells, each memory cell having a data input, a data output and a clock input, and receiving the output signal of a comparator at its data input, all the memory cells forming the memory stage receiving a similar signal, referred to as the clock signal, at their clock inputs, and PA1 a binary encoder which receives the outputs of the memory stage at its input and supplies the digital output signal of the converter. PA1 a ladder network of resistors arranged in series between a positive supply terminal and a negative supply terminal, which resistors produce a plurality of voltages referred to as reference voltages on the nodes between them, PA1 stages referred to as folding stages, each comprising an array of comparators adapted to generate a signal referred to as folding signal, which signal varies as a quasi-sinusoidal function of the analog input voltage, and a signal which is the counterpart of this folding signal, PA1 a first and a second interpolation stage, the first one receiving the folding signals and the second one receiving their counterparts, each interpolation stage being made up of impedance elements, preferably resistors of equal value, arranged as a divider bridge in such a manner that the signals, referred to as sampling signals, generated across the elements of the first interpolation stage represent fractions of the folding signals, the signals generated by the second interpolation stage forming their counterparts, PA1 a cycle detector which receives the folding signals and their counterparts and supplies signals referred to as cycle pointer signals and signals forming the counterparts thereof, enabling to identify that one of the cycles of the sampling signals which is significant of the value of the analog input voltage, PA1 a first memory stage comprising memory elements referred to as memory cells, each memory cell having two data inputs, a data output and a clock input, and receiving at its data inputs a sampling signal and its counterpart, all the memory cells forming the first memory stage receiving a similar signal, referred to as the clock signal, at their clock inputs, PA1 a second memory stage comprising memory cells, each memory cell receiving at its data inputs a cycle pointer signal and its counterpart, all the memory cells forming the second memory stage receiving the clock signal at their clock inputs, PA1 a binary encoder which receives the outputs of the memory stages at its input and supplies the digital output signal of the converter,
2. Description of Related Art
Such an analog-to-digital converter, generally referred to as a parallel converter, is described in the article "An 8-bit Video ADC Incorporating Folding and Interpolation Techniques" by Messrs. Rob E. Van de Grift, Ivo W. J. M. Rutten and Martien Van der Veen, published in the IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, of December 1987.
The memory cells used in this converter exhibit metastability problems in fields of use where the sampling frequency, which is defined as the number of times per second that a digital representation of the analog input voltage is latched, is high, i.e. when it approximates a limit frequency which is intrinsically defined by the fabrication process used for the implementation of the circuit. Indeed, the transition from analog to digital takes place when the states of the comparator outputs, which are analog signals, are loaded into the memory cells, whose digital outputs are switched at the rate imposed by the clock signal. The statistical theory of metastability reveals that the probability that an error occurs during the storage of an analog signal which exhibits a transient state increases strongly as the clock frequency, which controls the memory cell in which said analog signal is to be loaded, increases. As a matter of fact, it is found that if Fl is the intrinsic limit frequency imposed by the fabrication process, the error probability is of the order of exp (1-Fl/F). In the case of the analog-to-digital converter described in the article "An 8-bit Video ADC Incorporating Folding and Interpolation Techniques" the frequency of the signal which clocks the memory cells is equal to the sampling frequency Fe. The probability that an error due to metastability phenomena occurs during latching of the comparator output states is then of the order of exp (1-Fl/Fe).